The present invention relates generally to logic circuits, and more particularly to an apparatus for transforming differential mode signals into single ended signals with reduced power consumption.
When high-speed and low voltage swing data transfer is needed, differential signaling (also commonly referred to as double ended signals), wherein signals are carried on two conductors and the signal is defined as the difference in the two signals. Differential signaling is perhaps the most robust and promising signaling concept. Current mode logic (CML), a design technique commonly used in high speed signaling applications such as communications chips and routers, uses differential signaling.
CML is widely used in high-speed applications due to its relatively low power consumption and low supply voltage when compared to other types of logic, such as emitter coupled logic (ECL). CML is also considerably faster than CMOS logic due to its lower voltage swings. CML also has an added advantage of the capability of being fabricated using CMOS fabrication technology.
One advantage that CMOS logic has over CML is that in a CML circuit, there can be current flow a standby state, while in CMOS logic, no current flows in the standby state. Therefore, CML circuits will typically use more power than CMOS logic circuits.
However, since CML circuits and CMOS logic circuits may be created on the same substrate, it is possible to combine CML and CMOS logic circuits into one design. Thus, the high-speed advantages of CML circuits may be exploited where there is a need for high-speed switching, while CMOS logic""s low power consumption is available when the utmost high-speed is not required.
Unfortunately, CML circuits use differential signaling while CMOS logic circuits use single ended signals, wherein signals are carried on a single conductor. Therefore, a conversion between a CML circuit""s differential signals to a CMOS logic circuit""s single ended signal is needed.
A commonly used solution uses a CML differential mode to single ended mode signal converter with one or more single ended buffers (or inverters) to perform the conversion from differential signaling to single ended signaling. It is typical to turn off the CML circuit""s reference current source in order to reduce power consumption when the conversion is not needed or when the overall circuit is in standby.
One disadvantage of the prior art is that when the CML circuit""s reference current source is turned off, the gates of the transistors in the single ended buffer are left floating. This may result in an undefined input at the single ended buffer hence an undefined output is present at the output of the single ended buffer.
A second disadvantage of the prior art is that when there is an undefined input at the single ended buffer, it is probable that current will flow when the circuit is in standby since the output of the single ended buffer will change depending on its input. Thereby increasing current consumption.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which present an apparatus for converting differential mode signals to single ended signals with reduced power consumption
In accordance with a preferred embodiment of the present invention, a circuit comprising a current mode logic (CML) single ended converter having a differential mode input and a single ended output, the single ended converter containing circuitry to convert a differential mode signal into a single ended signal, and an output transistor coupled to the single ended output, the output transistor to set the single ended output to a logic state to a specified value.
In accordance with another preferred embodiment of the present invention, a circuit comprising a current mode logic (CML) single ended converter having a differential mode input and a single ended output, the single ended converter used for converting a differential mode signal into a single ended signal, and an output regulator circuit coupled to the single ended output, the output regulator circuit used for setting the single ended output to a logic state to a specified value when the CML single ended converter is in standby.
An advantage of a preferred embodiment of the present invention is that when the converter is in standby or is not being used, the input to the single ended buffer has a defined value. Therefore, there is a defined state at the input to the single ended buffer.
A further advantage of a preferred embodiment of the present invention is that since there is a defined state at the input to the single ended buffer, once the defined state is propagated through the buffer, there is no further state changes. Hence, there is no current flow when the converter is in standby.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.